Lecturer Profile |
Zheng Wang is currently an associate professor at Lancaster University (He will join the University of Leeds in July 2019). His main research interests are compiler technology and parallel program optimization. Zheng Wang received his Ph.D. from the University of Edinburgh in the UK in 2011. He previously worked on parallel programming models at IBM China Research Institute. More than 50 related papers have been published in high-level conferences and journals related to parallel computing and compilers. Part of his work won the best paper awards from ACM/IEEE PACT 2010, PACT 2017, CGO 2017, CGO 2019, and ACM/IEEE PACT 2010, CGO 2013 Best Report Award 2019 and other top international conferences, ACM CCS 2018 Best Paper Nomination. Relevant work was selected in more than 10 universities in the compilation course, including Carnegie Mellon University and the University of California, Berkeley. |
Lecture Abstract |
Developing an optimising compiler is a highly skilled and arduous process and there is inevitably a software delay whenever a new processor is designed. It often takes several generations of a compiler to start to effectively exploit the processors' potential, by which time a new processor appears and the process starts again. This never-ending game of catch-up means that we rarely fully exploit a shipped processor and it inevitably delays time to market. As we move to multi- and many-core platforms, this problem increases. This talk will look at research undertaken in my group which uses machine learning to automatically learn how to design compiler optimisation heuristics. It will discuss some of our award-winning studies that use deep learning to generate synthetic benchmarks and to automate the design process of compiler optimisation heuristics. |
