| Lecturer Profile |
Partha Pratim Pande is a Professor and holder of the Boeing Centennial Chair in computer engineering at the school of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. His current research interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks, and hardware accelerators for biocomputing. Dr. Pande currently serves as the Editor-in-Chief (EIC) of IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and Associate Editor-in-Chief (A-EIC) of IEEE Design and Test (D&T). He is on the editorial boards of IEEE Transactions on VLSI (TVLSI), ACM Journal of Emerging Technologies in Computing Systems (JETC) and Sustainable Computing: Informatics and Systems (SUSCOM). He was the technical program committee chair of IEEE/ACM Network-on-Chip Symposium 2015. He also serves in the program committee of many reputed international conferences. He has won the NSF CAREER award in 2009. He is the winner of the Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013. |
| Lecture Abstract |
The continuing progress and integration levels in silicon technologies make complete end-user systems on a single chip possible. This massive level of integration makes modern many core chips all pervasive in domains ranging from weather forecasting, astronomical data analysis, and biological applications to consumer electronics and smart phones. Network-on-Chips (NoCs) have emerged as communication backbones to enable a high degree of integration in many core platforms. Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop communications, wherein the data transfer between far-apart blocks causes high latency and power consumption. The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this talk, we will present design of the millimeter (mm)-wave wireless NoC architectures. We will present detailed performance evaluation and necessary design trade-offs for the small-world network-enabled wireless NoCs with respect to their conventional wireline counterparts in presence of both conventional CMP and emerging big data workloads. We will discuss how Machine Learning can be exploited to design energy efficient Wireless NoC architectures. We will finish this presentation by discussing how the wireless NoC paradigm can enable realization of datacenter-on-chip using heterogeneous processing cores. |
